library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity lab7 is
    Port (
	 	clk: IN STD_LOGIC;
		reset: IN STD_LOGIC;
		);
end lab7;

architecture Behavioral of lab7 is
	signal ct: unsigned (23 downto 0);

begin

	-- Handles the high speed clock and the reset.
	process(clk, reset)
	begin
		if reset = '1' then
			ct <= "000000000000000000000000";
		elsif rising_edge(clk) then
			ct <= ct + 1;
		end if;
	end process;

	-- Put something here to handle a clock of the correct speed.  Ct(0) is 12.5 MHz, so you don't want that.
	process(ct(0))
	begin
		if rising_edge(ct(0)) then
		end if;
	end process;

end Behavioral;