-- Vhdl test bench created from schematic count_quad.sch - Wed Feb 06 22:52:56 2002
--
-- Notes: 
-- 1) This testbench template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the unit under test.
-- Xilinx recommends that these types always be used for the top-level
-- I/O of a design in order to guarantee that the testbench will bind
-- correctly to the timing (post-route) simulation model.
-- 2) To use this template as your testbench, change the filename to any
-- name of your choice with the extension .vhd, and use the "Source->Add"
-- menu in Project Navigator to import the testbench. Then
-- edit the user defined section below, adding code to generate the 
-- stimulus for your design.
--
LIBRARY ieee;
LIBRARY UNISIM;
LIBRARY XilinxCoreLib;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE UNISIM.Vcomponents.ALL;
ENTITY testbench IS
END testbench;
ARCHITECTURE behavioral OF testbench IS 

   COMPONENT count_quad
   PORT( acurrent	:	IN	STD_LOGIC; 
          alast	:	IN	STD_LOGIC; 
          bcurrent	:	IN	STD_LOGIC; 
          blast	:	IN	STD_LOGIC; 
          clk_quad	:	IN	STD_LOGIC; 
          count	:	OUT	STD_LOGIC_VECTOR (7 DOWNTO 0));
   END COMPONENT;

   SIGNAL acurrent	:	STD_LOGIC;
   SIGNAL alast	:	STD_LOGIC;
   SIGNAL bcurrent	:	STD_LOGIC;
   SIGNAL blast	:	STD_LOGIC;
   SIGNAL clk_quad	:	STD_LOGIC;
   SIGNAL count	:	STD_LOGIC_VECTOR (7 DOWNTO 0);

BEGIN

   UUT: count_quad PORT MAP(
		acurrent => acurrent, 
		alast => alast, 
		bcurrent => bcurrent, 
		blast => blast, 
		clk_quad => clk_quad, 
		count => count
   );

-- *** Test Bench - User Defined Section ***
   tb : PROCESS
	BEGIN
		-- Don't start the clock until initialization in other processes is done.
		wait for 100 ns;
		CLOCK_LOOP : LOOP
			-- Simply run the clock.  I use a 10 MHz clock just to get more cycles
			--		in the same amount of simulator runtime.
			clk_quad <= '0';
			WAIT FOR 50 ns;
			clk_quad <= '1';
			WAIT FOR 50 ns;
		END LOOP CLOCK_LOOP;
	END PROCESS;

	ql: PROCESS
	BEGIN
		alast <= '0';
		blast <= '0';
		wait for 50 ns;
		ql_loop: LOOP
			-- There is a single D flip flop between acurrent and alast.  Each time
			--		the quadrature clock ticks, this copies the value of the current
 		   --		signals to the last signals.
			wait until clk_quad = '1';
			alast <= acurrent;
			blast <= bcurrent;
		END LOOP ql_loop;
	END PROCESS;

	qc: PROCESS
	BEGIN
		acurrent <= '0';
		bcurrent <= '0';
		wait until clk_quad = '1';
		qc_loop: LOOP
			-- Simple loop to count in the positive direction.
			acurrent <= '1';
			wait for 234 ns;
			bcurrent <= '1';
			wait for 123 ns;
			acurrent <= '0';
			wait for 345 ns;
			bcurrent <= '0';
			wait for 222 ns;
		END LOOP qc_loop;
	END PROCESS;

-- *** End Test Bench - User Defined Section ***

END;